The present application is based on Japanese priority application No.11-57601 filed on Mar. 4, 1999, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to semiconductor devices and more particularly to the fabrication process of a semiconductor memory device having a ferroelectric film.
Semiconductor memory devices such as DRAMs or SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory. On the other hand, DRAMs or SRAMs are volatile in nature and the information held therein is lost when the electric power is turned off. Thus, in order to store programs or data, conventional computers or other information processing apparatuses have used a magnetic disk device as a large-capacity, non-volatile storage device.
A magnetic disk device, however, has a drawback in that it is bulky and mechanically fragile. Further, there are additional drawbacks such as large power consumption and slow access speed.
In view of the foregoing various drawbacks of magnetic disk devices, there is a proposal to use a semiconductor non-volatile memory device such as EEPROM or flash memory as the non-volatile storage device of computers. An EEPROM or a flash memory has a floating gate electrode and stores information in the floating gate electrode in the form of electric charges. Particularly, a flash-memory has a cell structure similar to that of a DRAM and is suitable for use in constructing a large-scale integrated circuit.
Meanwhile, such EEPROM or flash memory has a drawback in that it takes time to write information into the memory device, as the writing of information is achieved by injection of hot electrons into the floating gate electrode through a tunneling insulation film. Further, there arises a problem that the tunneling insulation film becomes deteriorated when reading or writing of information is conducted repeatedly. When the tunneling insulation film has become deteriorated, writing or erasing of information becomes unreliable.
On the other hand, there is a different type of semiconductor non-volatile memory device called ferroelectric semiconductor memory (FeRAM), in which information is stored in a ferroelectric film in the form of spontaneous polarization. An FeRAM includes a single MOSFET as a memory cell transistor and a memory cell capacitor similar to a conventional DRAM, except that the dielectric film in the memory cell capacitor is replaced with a ferroelectric film such as PZT (Pb(Zr,Ti)O3), PLZT(Pb(Zr,Ti,La)O3), BST ((Ba,Sr)TiO3) or SBT(SrBi2Ta2O3). Thus, an FeRAM has a structure suitable for constructing a large-scale integrated circuit with a high integration density.
As noted above, writing of information is achieved in an FeRAM by controlling the spontaneous polarization of the ferroelectric capacitor, wherein the control of the spontaneous polarization is achieved by applying an electric field to the ferroelectric film constituting the ferroelectric capacitor. Thus, an FeRAM has an inherently high operational speed, which is faster than an EEPROM or a flash memory, in which writing is achieved by injection of hot-electrons, by a factor of 1,000 or more. Further, the electric power consumption is reduced by a factor of about {fraction (1/10)} in an FeRAM. Furthermore, an FeRAM, not using a tunneling insulation film, has an advantageous feature of long life-time, longer than a flash memory by a factor of 10,000.
FIG. 1 shows the construction of a conventional FeRAM.
Referring to FIG. 1, an FeRAM 10 is constructed on a p-type Si substrate 11, on which an active region is defined by a field oxide film 12. The active region is covered by a gate oxide film not designated in FIG.1 by a reference numeral, and a gate electrode 13 is provided on the gate oxide film in corresponding to a word line of the FeRAM. Further, diffusion regions 11A and 11B of the n+-type are formed in the substrate 11 at both lateral sides of the gate electrode 13 as source and drain regions of the memory cell transistor. In the substrate 11, a channel region is formed between the foregoing diffusion regions 11A and 11B.
It should be noted that the gate electrode 13 is covered by a CVD-oxide film 14 deposited on the substrate 11 so as to cover the active region, and the CVD-oxide film 14 in turn is covered by a planarizing interlayer insulation film 15. The interlayer insulation film 15 is formed with a contact hole 15A exposing the diffusion region 11B, and a WSi plug 16 is formed such that the WSi plug 16 fills the contact hole 15A.
Further, an adhesion layer of Ti/TiN structure (not shown) is formed on the interlayer insulation film 15 including the part where the plug 16 is exposed, and a lower electrode 17 of Pt, and the like, is formed on the adhesion layer thus formed. Further, a ferroelectric film 18 of PZT or PLZT is formed on the lower electrode 17, and an upper electrode 19 of Pt is formed on the ferroelectric film 18.
The lower electrode 17, the ferroelectric film 18 and the upper electrode 19 form together a ferroelectric capacitor C, wherein the ferroelectric capacitor is covered by a CVD-oxide film 21 including a side wall part thereof, and an interconnection pattern 20 makes an electrical contact with the upper electrode 19 via a contact hole formed in the CVD-oxide film 21. Further, the entirety of the ferroelectric capacitor C is covered by an interlayer insulation film 22.
The interlayer insulation film 22 includes a contact hole 22A exposing the diffusion region 11A, and a bit line pattern 23 of Al or an Al-alloy is formed on the interlayer insulation film 22 so as to make an electrical contact with the diffusion region 11A at the contact hole 22A.
FIG. 2 shows a unit cell of a PZT crystal used in the FeRAM 10 of FIG.1 as the ferroelectric film 18.
Referring to FIG. 2, the crystal of PZT has a perovskite structure, which is characterized by a phase transition in which a Ti or Zr atom occupying the site coordinated by O atoms undergoes a displacement in the direction of the c-axis. Thereby, the direction of the displacement depends on the direction of the external electric field applied to the PZT crystal, and thus, the PZT crystal exhibits a spontaneous polarization as represented in FIG. 3. Thus, by applying a predetermined writing voltage across the lower electrode 17 and the upper electrode 19, it is possible to reverse the polarization of the PZT crystal constituting the ferroelectric film 18. In other words, it is possible to write desired binary information into the ferroelectric film 18 by applying such a predetermined writing voltage.
When reading out the binary information thus written into the FeRAM 10 of FIG. 1, the word line, and hence the gate electrode 13 of the memory cell transistor, is activated, and the voltage appearing at the bit line electrode 23 as a result of conduction of the channel region, is detected.
Referring to the hysteresis loop of FIG. 3, the height of the loop at the zero electric field strength is called the switching electric charge QSW. The larger the value of the quantity QSW, the better the reliability of information retention in the FeRAM 10. Further, the electric field necessary for wiring information into the FeRAM 10 decreases with increasing values of QSW. Thereby, the FeRAM 10 can be driven at a low voltage. Thus, in the FeRAM 10 of FIG. 1, it is desired to maximize the value of QSW of the ferroelectric film 18.
In order to obtain the spontaneous polarization represented in FIG. 3 for the FeRAM 10 of FIG. 1, it is necessary to crystallize the ferroelectric film 18 in an oxidizing atmosphere at the temperature of at least 600xc2x0 C. Thus, it has been practiced to form the lower electrode 17 by a refractive metal such as Pt, which shows a low reactivity against O2 and maintains a low resistivity even when processed in such an oxidizing atmosphere. On the other hand, such a lower electrode 17 formed of Pt has a drawback in that it cannot block the diffusion of oxygen atom (O) or Pb effectively, and the ferroelectric film 18 tends to become depleted in Pb or O. In such a non-stoichiometric composition, the ferroelectric film 18 cannot provide the desired spontaneous polarization represented in FIG. 3.
In order to eliminate the foregoing problem, there is a proposal, related to the ferroelectric capacitor C of FIG. 1, to form the lower electrode 17 by a lower electrode film part 17A of IrO2 and an upper electrode film part 17B of Pt as represented in FIG. 4A. Further, there is a proposal as represented in FIG. 4B, in which the upper electrode 19 is formed of a lower electrode film part 19A of IrO2 and an upper electrode film part 19B of Pt formed on the lower electrode film part 19A. In the construction of FIG. 4B, the problem of formation of oxygen defects in the ferroelectric film 18 is effectively eliminated by forming the IrO2 film 19A adjacent to the ferroelectric film 18.
Unfortunately, it is known, in the ferroelectric capacitor C of such a construction, that there occurs a substantial fatigue phenomenon in the ferroelectric film 18 as a result of repetition of polarizing steps, in which and the magnitude of the residual polarization or inversion electric charges QSW becomes reduced with repetitive polarization steps, thus resulting in the fatigue. It is believed that such a fatigue is caused by the fact that the IrO2 film cannot prevent the oxygen defect formation in the ferroelectric film 18 when the polarizing steps are repeated and possibly the formation of a dielectric phase between IrO2 and PZT.
In the ferroelectric capacitor C of FIG. 4A or 4B, there has been another problem in that it is difficult to obtain a satisfactory imprint performance. The reason for this unsatisfactory result is attributed to the oxygen defect formation in the ferroelectric film 18 which occurs at the interface to the Pt electrode. Further, associated with the miniaturization of the FeRAM, there occurs a problem in that the electric performance of the film 18 is degraded rapidly with decrease in the thickness of the ferroelectric film 18.
In view of the situation noted above, the inventor of the present invention has proposed a ferroelectric capacitor that uses SrRuO3 (SRO) for the upper electrode 19 in the construction of FIG. 1. According to the previous proposal of the inventor, a ferroelectric capacitor having an excellent performance with regard to the fatigue and reliability is obtained. Further, the ferroelectric capacitor maintains an excellent electrical performance even in the case wherein the thickness of the ferroelectric film 18 is reduced.
In order to fabricate such a ferroelectric capacitor that uses SrRuO3 in a form suitable for use in the FeRAM of FIG. 1, it is necessary to establish the art of dry-etching a SrRuO3 film. A process of dry-etching a SrRuO3 film has been established in a conventional RF etcher in the presence of Cl2, Ar and O2 gases.
In the ferroelectric capacitor that uses SrRuO3 for the upper electrode, there has been a further problem in that, while the performance of the capacitor is significantly improved over the conventional ferroelectric capacitor with regard to fatigue, the performance is not yet sufficient for use as a capacitor in a practical semiconductor device.
At present, the mechanism of the foregoing insufficient improvement with regard to the fatigue of the ferroelectric capacitor is not well understood. It is suspected that Sr atoms in the SrRuO3 electrode migrate to the grain boundary of the ferroelectric film such as a PZT film at the time of the annealing process, and the Sr atoms thus migrated cause a further diffusion, at the time of the fatigue test conducted on the ferroelectric capacitor. As a result of the diffusion, there may be formed a conductive channel of a compound such as SrPbO3 in the ferroelectric film. It should be noted that SrPbO3 is a material with a resistance of a semiconductor. When such a semi-conductive channel is formed in the ferroelectric capacitor, the ferroelectric capacitor may undergo a short-circuit.
In the investigation conducted by the inventor of the present invention and constituting the foundation of the present invention, it was discovered that the problem of short-circuit and associated degradation of reliability of the ferroelectric capacitor appears conspicuously when the thickness of the ferroelectric film has exceeded a value of 70 nm.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a ferroelectric capacitor having an upper electrode of a perovskite oxide, wherein the fabrication thereof is substantially facilitated and the performance thereof substantially improved with regard to leakage current, fatigue and imprinting.
Further, the present invention provides a semiconductor device having such a ferroelectric capacitor and a fabrication process thereof.
Another object of the present invention is to provide a ferroelectric capacitor, comprising:
a lower electrode;
a ferroelectric capacitor insulation film provided on said lower electrode; and
an upper electrode provided on said ferroelectric capacitor insulation film, said upper electrode including an oxide layer having a perovskite structure,
said ferroelectric capacitor insulation film having a composition of PZT,
wherein said ferroelectric capacitor insulation film contains an excess amount of Pb with respect to a stoichiometry of PZT.
According to the present invention, the amount of Pb existing at the grain boundary of the PZT ferroelectric capacitor insulation film is optimized by adjusting the composition of the PZT film. More specifically, by setting the composition of the PZT film so as to contain an excess amount of Pb with respect to the stoichiometric composition of PZT, the amount of the Pb atoms existing on the grain boundary is also optimized and the Pb atoms thus concentrated on the grain boundary effectively suppress the diffusion of the Sr atoms from the SrRuO3 upper electrode into the PZT capacitor insulation film. Thereby, the performance of the ferroelectric capacitor is improved substantially, particularly with regard to the fatigue characteristic.
Another object of the present invention is to provide a ferroelectric capacitor, comprising:
a lower electrode;
a ferroelectric capacitor insulation film provided on said lower electrode; and
an upper electrode provided on said ferroelectric capacitor insulation film, said upper electrode including an oxide layer having a perovskite structure provided on said ferroelectric capacitor insulation film,
said oxide layer having a composition of SrRuO3 and a thickness of about 30 nm or less.
According to the present invention, the performance of the ferroelectric capacitor is improved substantially with regard to the fatigue characteristic, by merely interposing a thin layer of SrRuO3 between the PZT ferroelectric capacitor insulation film and the Pt upper electrode as a part of the foregoing upper electrode, wherein the leakage characteristic of the ferroelectric capacitor is improved substantially by setting the thickness of the SrRuO3 layer to be less than about 30 nm. In view of facilitating the dry etching process of the upper electrode that includes a layer of SrRuO3, it is preferable to set the thickness of the SrRuO3 layer as thin as possible for facilitating the dry etching process applied to the upper electrode.
Another object of the present invention is to provide a method of fabricating a ferroelectric capacitor, comprising the steps of:
depositing a lower electrode on a substrate;
forming a ferroelectric capacitor insulation film on said lower electrode;
forming an upper electrode of an oxide layer having a perovskite structure; and
applying, after said step of forming said upper electrode, an annealing process at a temperature of about 600xc2x0 C. or more.
According to the present invention, the fatigue characteristic of the ferroelectric capacitor is improved substantially by conducting the annealing process at the temperature of about 600xc2x0 C. or more.